For application of voltage to a semiconductor device, depletion layers are formed in an active region that actively functions as a semiconductor element, and a concentration of electric fields occurs at a boundary between the depletion layers, thereby decreasing withstand voltage of the semiconductor device. Thus, a terminal region of a conductivity type opposite to a conductivity type of a semiconductor layer is provided on an outer peripheral side of the active region, so that a p-n junction between the semiconductor layer and the terminal region causes the depletion layers to spread, and the concentration of electric fields is relieved, which allows for an increase in the withstand voltage of the semiconductor device.
A field limiting ring (FLR) structure including a plurality of ring-shaped implantation regions that surround an active region is widely applied to conventional semiconductor devices, as a structure of a terminal region that increases withstand voltage of the semiconductor devices. In the FLR structure, an interval between the rings gradually increases toward an outer peripheral side of the semiconductor devices to gradually reduce an impurity concentration per unit area toward the outer peripheral side, thereby producing semiconductor devices that can obtain high withstand voltage by effectively relieving electric fields (see Patent Document 1, for example).